package cil

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package cil

cil
- Alpha
- Availexps
- Availexpslv
- Bitmap
- Cabs
- Cabs2cil
- Cabshelper
- Cabsvisit
  - cabsVisitor
  - nopCabsVisitor
- Callgraph
- Canonicalize
- Cfg
- Check
- Cil
- Cilint
- Cillower
- Ciloptions
- Ciltools
- Cilutil
- Cilversion
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- Cparser
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- Dataflow
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- Dominators
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  - volatileFinderClass
- Feature_config
- Formatcil
- Formatlex
- Formatparse
- Frontc
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- Llvm
- Llvmgen
  - llvmGenerator
  - llvmGeneratorClass
- Llvmssa
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  - logWriteVisitor
- Longarray
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  - AliasInfo
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  - EasyAlias
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    A
    
    callGraphVisitor
  - MakePartial
    
    A
    
    C
    
    LabelSet
    
    S
  - NeculaFolding
    
    A
    
    IntMap
    
    findLval
    
    rewriteExpClass
  - PartialAlgorithm
  - PtranalAlias
  - Symex
  - callBBVisitor
  - globalConstVisitor
  - vidVisitor
- Patch
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  - ExpIntHash
  - NullSolver
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  - PredAbst
    
    PA
    
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    aliasFinderClass
    
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    funcSigMakerClass
    
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    returnFinderClass
    
    viFinderClass
  - SOLVER
  - Solver
    
    T
  - TRANSLATOR
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    Map
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- Ptranal
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  - IOS
  - RD
  - ReachingDef
  - rdVisitorClass
- Rmtmps
- Setp
  - Make
    
    Ord
  - PolyOrderedType
  - S
- Sfi
  - sfiVisitorClass
- Simplemem
  - simpleVisitor
- Simplify
- Ssa
- Stats
- Trace
- Uref
- Usedef
  - VS
  - useDefVisitorClass
- Util
- Whitetrack

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type cfgInfo = {

name : string;
start : int;
size : int;
blocks : cfgBlock array;
successors : int list array;
predecessors : int list array;
mutable nrRegs : int;
mutable regToVarinfo : Cil.varinfo array;

}

and cfgBlock = {

bstmt : Cil.stmt;
instrlist : instruction list;
mutable livevars : (reg * int) list;
mutable reachable : bool;

}

and instruction = reg list * reg list

and reg = int

type idomInfo = int array

and dfInfo = int list array

and oneSccInfo = {

nodes : int list;
headers : int list;
backEdges : (int * int) list;

}

and sccInfo = oneSccInfo list

val add_ssa_info : cfgInfo -> unit

val stronglyConnectedComponents : cfgInfo -> bool -> sccInfo

val prune_cfg : cfgInfo -> cfgInfo