Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.
if and switch control constructs are provided. ($==) is used for assignment.
Code is written as lists of assignments, if and control statements.
variables;
let var = wire (zero 8) in
let var = reg r_sync enable 8 inassignment;
var $== exp;if statements;
if_ condition [ ... ] [ ... ]switch statements;
switch condition [
consti 3 0 [ ... ];
consti 3 1 [ ... ];
consti 3 2 [ ... ];
consti 3 3 [ ... ];
]signals;
let (s:signal) = q (v:guarded) incompilation;
compile [ ... ]example;
let state = reg r_sync enable 2 in
let a = wire 8 in
compile [
if_ a#q ==: consti 8 4 [
a $== consti 8 2
] [
switch (q state) [
(consti 2 0) [
a $==. 3;
state $== const 2 1;
];
(consti 2 1) [
a $==. 2;
state $== const 2 2;
];
(consti 2 2) [
a $==. 1;
state $== const 2 3;
];
(consti 2 3) [
a $==. 0;
state $== const 2 4;
]
]
];
let state = state#q in
let a = a#q in
....val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.ttype always = tmodule Variable : sig ... endThe type of variables in guarded assignments. Variables may be asychronous wires, or synchronous regs. The current value of the variable may be accessed through the value field below.
type 'a case = 'a * t Base.List.ttype 'a cases = 'a case Base.List.tval if_ : Signal.t -> t Base.List.t -> t Base.List.t -> tif statement
val elif : Signal.t -> t Base.List.t -> t Base.List.t -> t Base.List.telse if branch
val when_ : Signal.t -> t Base.List.t -> tif sel then ... else
val unless : Signal.t -> t Base.List.t -> tif sel then else ...
val proc : t Base.List.t -> tAllows sequences of expressions to be inserted into the code; a syntactic nicety.
val (<--) : Variable.t -> Signal.t -> tassignment
val (<--.) : Variable.t -> Base.Int.t -> tassignment with an integer constant - width is inferred
module State_machine : sig ... endval compile : t Base.List.t -> Base.Unit.tcompile to structural code