package hardcaml

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package hardcaml
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Module
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Class type
type port_list = Port_list.t
type task = Base.unit -> Base.unit
val create : in_ports:port_list -> out_ports_before_clock_edge:port_list -> out_ports_after_clock_edge:port_list -> internal_ports:port_list -> reset:task -> cycle_check:task -> cycle_before_clock_edge:task -> cycle_at_clock_edge:task -> cycle_after_clock_edge:task -> lookup_signal:(Signal.Uid.t -> Bits.t Base.ref) -> lookup_reg:(Signal.Uid.t -> Bits.t Base.ref) -> assertions:Signal.t Base.Map.M(Base.String).t -> t_port_list
module Step : sig ... end
val modify : ('i, 'o) t -> (Side.t * Step.t * task) Base.list -> ('i, 'o) t
val coerce : (port_list, port_list) t -> to_input:(port_list -> 'i) -> to_output:(port_list -> 'o) -> ('i, 'o) t
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