package hardcaml_axi

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package hardcaml_axi
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AXI4 Interface specifications.

See Xilinx User Guide ug1037 for full documentation.

Summary;

  • AXI4 is for memory-mapped interfaces and allows high throughput bursts of up to 256 data transfer cycles with just a single address phase.
  • AXI4-Lite is a light-weight, single transaction memory-mapped interface. It has a small logic footprint and is a simple interface to work with both in design and usage.
  • AXI4-Stream removes the requirement for an address phase altogether and allows unlimited data burst size. AXI4-Stream interfaces and transfers do not have address phases and are therefore not considered to be memory-mapped.
module type Bus_config = sig ... end
module type Stream_config = Stream.Config
module Address_space_decoder : sig ... end

Construction of address space decoders. This supports a slower but more complete full address space decoder and the faster but incomplete partial address decoder.

module Internal_bus : sig ... end
module Lite : sig ... end

AXI4-lite master/slave interface

module Lite_ports : sig ... end
module Stream : sig ... end

AXI4-stream source/dest interface.

module Register_bank : sig ... end
module Register_mode : sig ... end

Write configuration of a register from the core interface.

module Slave_with_data : sig ... end
module C_register_interface : sig ... end

C-code generators for a memory-mapped register space.

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