package hardcaml_of_verilog

You can search for identifiers within the package.

in-package search v0.2.0

hardcaml_of_verilog
- Hardcaml_of_verilog
  - Circuit_to_json
  - Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    V
    
    Bit
    
    Cell
    
    V
    
    Connection
    
    V
    
    Direction
    
    Int_or_string
    
    Module
    
    V
    
    Netname
    
    V
    
    Parameter
    
    V
    
    Port
    
    V
    
    Port_direction
    
    V
  - Netlist
    
    Bit
    
    Bus
    
    Bus_names
    
    Cell
    
    Module
    
    Parameter
    
    Port
    
    Fields
    
    Direct
  - Ocaml_module
    
    Rebuild_interfaces
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    X
  - Pass
  - Verilog_circuit
  - Verilog_design
    
    Crunched
    
    Define
    
    Define_value
    
    Defines
    
    Embedded_files
    
    Module
    
    Parameter
    
    Parameters
  - With_interface
    
    Make
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
hardcaml_of_verilog.port
- Hardcaml_port_verilog
  - Make
    
    X

Legend:
Library
Module
Module type
Parameter
Class
Class type

type t = {

name : Base.string;
inputs : Bus.t Port.t Base.list;
outputs : Bus.t Port.t Base.list;
cells : Cell.t Base.list;
bus_names : Bus_names.t;

}

val sexp_of_t : t -> Sexplib0.Sexp.t

val sanitize_instance_names : t -> t