package hardcaml_verify

Control comparison of instantiation inputs and outputs.

They should either be equal or the left should be a subset of the right.

This is allowed to help comparing with verilog designs. In verilog an input or output may be specified without a signal, and when converting with Hardcaml_of_verilog they will not exist in the instantiated sub-circuit. Care should be taken to ensure the undriven ports do not effect the operation of the design ie. try to avoid it, but it is unfortunately somewhat inevitable with some external verilog code.